In a computer system, the operating voltage supplied to the processor, such as the central process unit (CPU) or graphic process unit (GPU), is determined by a dynamic voltage identification (VID) code produced based on the requirement of the processor.
FIG. 1 is a block diagram of a prior power supply. A VID code is generated by a processor 103 in accordance to its required operating voltage. A reference adjusting circuit 101 receives the VID code, and based on the VID code, adjusts a previously set reference voltage Vrefint, and outputs the adjusted reference voltage Vref.
A voltage regulator 102 comprising at least one switch receives the adjusted reference voltage Vref, and converts an input voltage Vin into an output voltage Vout in accordance to the adjusted reference voltage Vref. The output voltage Vout is used as the operating voltage of the processor 103. Generally, the output voltage Vout is fed back and compared with the adjusted reference voltage Vref, so as to control the ON and OFF switching of the switches in the voltage regulator 102.
In some applications, the reference adjusting circuit 101 further receives a slew rate command together with the VID code from the processor 103. The slew rate command is used to indicate the required transition rate of the operating voltage. In the voltage regulation standard, VR12, set by Intel, there are 3 different slew rates: fast, slow, and decay.
When a slew rate command SetVID_Fast or SetVID_Slow and a VID code are received, the reference adjusting circuit 102 ramps up/down the previously set reference voltage Vrefint in a controlled rate until the adjusted reference voltage Vref reaches a target value corresponding to the VID code. The target value may be equal to the required operating voltage.
The decay slew rate command SetVID_Decay is normally used for VID down transition. In the prior art, when a SetVID_Decay command and a VID code are received, the reference adjusting circuit 102 directly changes the previously set reference voltage Vrefint into a target value corresponding to the VID code without controlling the slew rate. The switches in the voltage regulator 102 will all be shut down and the output voltage Vout decays at a rate proportional to the load current.
However, if the processor 103 sends out a SetVID_Fast or SetVID_Slow command with a new VID code before the output voltage Vout decays to reach the previously set reference voltage Vrefint, the switches in the voltage regulator 102 will be activated again. The reference adjusting circuit 102 will ramp up/down the previously set reference voltage Vrefint in a controlled rate. If the output voltage Vout is much bigger than the adjusted reference voltage Vref at the time, an undershoot of the output voltage Vout will be generated and the switches in the voltage regulator 102 may be damaged if there is no reverse current protection for the switches.
FIG. 2 is a waveform of the prior power supply shown in FIG. 1. At t=t0, the reference voltage Vref is VREF0 and the output voltage Vout is equal to the reference voltage Vref. At t=t1, a SetVID_Decay command and a first VID code VID1 are sent to the reference adjusting circuit 101 by the processor 103. The reference voltage Vref is directly changed into a first target value VREF1 corresponding to VID1. The switches in the voltage regulator 102 are all shut down and the output voltage Vout decays at a rate proportional to the load current.
At t=t2, a SetVID_Fast command and a second VID code VID2 are sent to the reference adjusting circuit 101, wherein VID2 is larger than VID1. The switches in the voltage regulator 102 are activated again and the reference voltage Vref is ramped up in a controlled rate. Since the output voltage Vout is much bigger than the reference voltage Vref at t=t2, an undershoot of the output voltage Vout is generated. The output voltage Vout is increased along with the reference voltage Vref after then. At t=t3, the reference voltage Vref and the output voltage Vout reach a second target value VREF2 corresponding to VID2.